1. Field of the Invention
The present invention relates to the field of analog to digital conversion. Specifically, the present invention relates to pipelined multistage analog to digital converters.
2. Discussion of the Related Art
For high conversion speeds several techniques are currently used, such as flash, multi-step, pipeline, interpolating, and time-interleaved successive approximation. Out of these, the pipelined techniques offer the best trade-off between complexity, silicon area, and power consumption on the one hand and conversion speed on the other hand.
A typical K-bit pipelined converter stage has the block diagram of FIG. 1. The analog input to stage I 100 is the residue Vres.sub.i-1 from the preceding stage i-1. The analog input Vres.sub.i-1 is sampled and held by a sample and hold circuit 101. The sample and hold circuit 101 latches the potentially time varying analog input level Vres.sub.i-1 and maintains its sampled analog output 102 at a constant analog level for a certain hold time t.sub.hold. The sampled analog output 102 is converted into a K-bit digital code D.sub.i [K-1:0] by the analog to digital subconverter 103. This K-bit digital code D.sub.i [K-1:0] is output by stage i 100 and represents K raw digital output bits of the overall pipelined converter (not shown). Less significant output bits are generated by subsequent stages of the pipelined analog to digital converter. In order to generate less significant output bits, the latched analog input level 102 must be reduced by an analog amount which exactly corresponds to the K-bit digital code D.sub.i [K-1:0] extracted by the analog to digital subconverter 103. Therefore, a local K-bit digital to analog converter 104 is used to generate an analog voltage 105 which corresponds to the K-bit digital code D.sub.i [K-1:0]. This analog voltage 105 is subtracted from the latched analog input 102 by an analog subtractor 106. The analog residue 107 output by the analog subtractor 106 is analogous to a remainder in division-after each group of K output digits is produced, the remainder 107 is passed on to the next iteration. In order to allow each stage to be identical, the residue 107 is amplified by the radix of the stage by amplifier 108 to produce the output residue Vres.sub.i of stage i. For a K-bit binary converter stage, the appropriate amplification factor is 2.sup.K.
The resulting residue Vres.sub.i can be calculated from the following equation 1. EQU Vres.sub.i =2.sup.K (Vres.sub.i-1 -Vdac.sub.i) (1)
The linearity of the pipelined analog to digital converter is dependent upon the linearity of the first stage that produces the most significant digital output bits. Therefore, single bit analog to digital subconverters and digital to analog converters are very popular because of their inherent linearity. Single bit digital to analog converters are inherently linear because there is always a straight line that can be drawn between the two output voltages, which are typically a reference voltage and ground. Single bit analog to digital converters are essentially comparators. If the input voltage to the single bit analog to digital converter is greater than a threshold value, the digital output is one; in contrast, if the input voltage is less than the threshold value, the digital output is zero. By placing the threshold exactly in the center of the input voltage range, a single bit analog to digital converter (comparator) can be made perfectly linear. If K=1, the analog to digital subconverter 103 is a comparator, and the local digital to analog converter 104 has only two output values. The digital output extracted from the ith stage degenerates to a single bit D.sub.i. In this case, the ideal gain of the converter stage is 2, and the equation for the residue is given by the following equation. EQU Vres.sub.i =2Vres.sub.i-1 -D.sub.i Vref (2)
In equation 2, both the input residue Vres.sub.i-1 and the output residue Vres.sub.i exist within the range from 0 to +Vref, and the digital data D.sub.i can take only the values 0 or 1.
The circuit shown in FIG. 2A is typically used to generate the output residue Vres.sub.i when the converter pipeline is designed to pass a single-ended, rather than differential, residue from stage to stage. The circuit shown in FIG. 2A operates using a two-phase non-overlapping clock. During phase 1, switches S1A, S1B, and S1C are closed while switches S2A and S2B are open. During phase 2, switches S2A and S2B are closed while switches S1A, S1B, and S1C are open.
FIG. 2B illustrates the configuration of the circuit of FIG. 2A during phase 1 of the non-overlapping clocks. During phase 1, the switch S1C holds the operational amplifier 200 in a voltage follower configuration. When an ideal operational amplifier is operated in its linear region, the voltages at the plus input 202 and at the minus input 201 are always essentially equal to each other, because the gain of the operational amplifier is very large, usually on the order of 100,000 or more. An ideal operational amplifier therefore has an input-output characteristic determined by the following equation. EQU A*(Vin+-Vin-)=Vout (3)
Unfortunately, however, most real operational amplifiers are not ideal. Most real operational amplifiers have a non-zero offset. When both inputs are grounded, the output is not zero, but is some offset voltage Voffset. The effect of offset is that the input-output characteristic becomes the following. EQU A*(Vin+-Vin-)=Vout+Voffset (4)
Therefore, in this voltage follower configuration shown in FIG. 2A, the minus input 201 to the operational amplifier 200 settles to a level essentially equal to the operational amplifier offset voltage Voffset divided by the gain A. Since the gain A is very large, the voltage Vin- at the operational amplifier minus input 201 and at the output Vres.sub.i are approximately zero, and the effect of the offset voltage Voffset on the output of the operational amplifier 200 is essentially negated with almost no effect on the voltages of the capacitors C1 and C2. Thus, during the sampling phase, the following relations hold. EQU Vin+=0 (5A) EQU Vin-=Vres.sub.i .apprxeq.0 (5B)
As a consequence, during the sampling phase 1, the input voltage Vres.sub.i-1 is sampled through switches S1A and S1B across the positive terminals 203 and 204 of capacitors C1 and C2, respectively, while approximately zero is applied to the negative terminals 20B and 206 of the capacitors C1 and C2. The total voltage across capacitors C1 and C2 thus becomes the following. EQU VC1=VC2=Vres.sub.i-1 ( 6)
As shown in FIG. 2C, During the output phase 2 of the non-overlapping clocks, capacitor C1 is connected to the operational amplifier output Vres.sub.i through the switch S2A, and capacitor C2 is connected to D.sub.i Vref through the switch S2B.
An attractive feature of this circuit is that the offset voltage of the operational amplifier 200 is effectively canceled. During the hold phase 2, switch S2B connects D.sub.i Vref to the positive terminal of capacitor C2, and switch S2A connects the output Vres.sub.i to the positive terminal of capacitor C1. Let the voltages over time t across capacitors C1 and C2 be VC1(t) and VC2(t), respectively. If the switches S2A and S2B are closed at time t=0, then the following relations hold just at the time t=0- just prior to the switches S2A and S2B being closed. EQU VC1(0-)=VC2(0-)=Vres.sub.i-1 ( 7)
After the switches are closed at time t=0 and remain closed for a sufficient time, the following relations hold because the minus input Vin- 201 is always essentially at ground. EQU VC2(.infin.)=D.sub.i Vref (8)
The positive and negative terminals of an operational amplifier are designed to draw no current. Because the minus input 201 draws negligible current, the current i2 through capacitor C2 is the negative of the current i1 through capacitor C1. Because the capacitances of C1 and C2 are designed to be identical, any decrease in voltage across capacitor C2 causes a corresponding increase in the voltage across capacitor C1, and vice versa. Therefore, after a long time (at t=.infin.), the voltage across capacitor C1 is its initial value minus the change in voltage across capacitor C2. Therefore, the following relation holds. EQU VC1(.infin.)=VC1(0-)-[VC2(.infin.)-VC2(0-)] (9)
Substituting equations 7 and 8 into the above relation results in the following. EQU VC1(.infin.)=2Vres.sub.i-1 -D.sub.i Vref=Vres.sub.i ( 10)
This is the desired result shown in equation 2. However, the operational amplifier cannot supply infinite current at time t=0 in order to instantaneously change the voltages across capacitors C1 and C2 to reflect: the subtraction of D.sub.i *Vref. Instead, during the hold phase 2, the output at time t of the stage is the following. EQU Vres.sub.i (t)=Vres.sub.i-1 +(1-e.sup..beta.t/.tau.)(Vres.sub.i-1 -D.sub.i Vref) (11)
In the above equation, .tau./.beta. is the time constant of the operational amplifier driving the capacitances divided by the feedback ratio .beta.. As can be determined from equation 11, the operational amplifier 200 settles on its final output voltage as a decaying exponential with a time constant .tau./.beta.. Because it is not possible to wait forever until time t=.infin. to realize the final output voltage, there must be a some time t.sub.s at which the output Vres.sub.i (t) is deemed to be close enough to its final level Vres.sub.i (.infin.). Typically, an analog voltage error equal to one-quarter of a least significant bit is considered to be adequate, since an error at that level will not affect the resulting output code of the pipelined converter. The entire range of analog input is Vref wide. Therefore, the following inequality must hold. EQU 1-e.sup.-.beta.t/.tau. .gtoreq.1-.epsilon. (12)
where EQU .epsilon.=(1/4)(1/2.sup.N)=1/2.sup.N+2 ( 13)
In the above equations, .epsilon. represents the error fraction corresponding to one quarter of a least significant bit of an N-bit output code. Equations 12 and 13 can be combined and rewritten as the following. EQU e.sup.-.beta.t/.tau. .ltoreq.1/2.sup.N+2 ( 14)
Taking the natural logarithm of both sides results in the following. EQU .beta.t/.tau..ltoreq.(N+2)1n2 (15)
If the minimum time t which meets the above inequality is defined to be the settling time t.sub.s of the operational amplifier, then the following relation holds. EQU t.sub.s =(N+2)(.tau./.beta.)1n2 (16)
If the total period of the clock is T and is equally divided between the sampling phase 1 and the hold phase 2, then the following relation holds. ##EQU1##
By substituting 1/(2.pi.f.sub.u) for .tau., the unity gain bandwidth requirement of the operational amplifier is derived as the following f.sub.u. ##EQU2##
The disadvantage, however, of the circuit in FIGS. 2A, 2B, and 2C is that the operational amplifier 200 has to settle to within the required precision of the converter during both the sampling phase 1 and the hold phase 2 of the clock. Assuming an N-bit converter pipelined with a sampling period T, which is equally divided between the sampling and the hold phase of each stage, the required unity gain bandwidth f.sub.u of the operational amplifier can be calculated from equation 18 in which T/2 is the settling time t.sub.s, .beta. is the feedback gain, and N+2 is the required settling precision within 1/4 of a least significant bit. In this case, .beta. is 1/2 because the capacitances of capacitors C1 and C2 are equal, therefore C1/(C1+C2)=1/2.
As a typical example using equation 18, for a 12-bit 40 Megasample per second converter, the required operational amplifier bandwidth f.sub.u is almost 250 MHz. In a practical implementation, the settling time must be even less than T/2 to accommodate for the guard intervals between the non-overlapping phases. Using the same example, the settling time T/2 in a real implementation should be no more than 10 ns, requiring an operational amplifier bandwidth larger than 300 MHz.
Using conventional techniques, the overall clock period is constrained during both the sampling phase and the hold phase by the operational amplifier settling time, which defines the operational amplifier bandwidth. It is therefore desirable to design a pipelined analog to digital converter stage in which the duration of the sampling phase is not constrained by the operational amplifier settling time. Using such a converter stage, it would be desirable to construct a multistage pipelined analog to digital converter that takes advantage of the reduced sampling time requirement so as to have a shorter overall clock period without increasing the operational amplifier bandwidth requirement.